A posting on Twitter has revealed that Tiger Lake-U will feature a 50% larger L3 cache, to 12MB. It also indicated that the Willow Cove architecture doesn't have bfloat16 support.from Tom's Hardware https://ift.tt/305YfZa
Monday, 16 September 2019
Intel's Tiger Lake Growls: 10nm Chip Packs 50 Percent More L3 Cache and AVX-512
A posting on Twitter has revealed that Tiger Lake-U will feature a 50% larger L3 cache, to 12MB. It also indicated that the Willow Cove architecture doesn't have bfloat16 support.from Tom's Hardware https://ift.tt/305YfZa
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